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| a FEATURES Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 12-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 5 MHz Output: 70 dBc Differential Current Outputs: 2 mA to 20 mA Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V Power-Down Mode: 25 mW @ 5 V On-Chip 1.20 V Reference Single +5 V or +3 V Supply Operation Package: 28-Lead SOIC and TSSOP Edge-Triggered Latches APPLICATIONS Communication Transmit Channel: Basestations (Single/Multichannel Applications) ADSL/HFC Modems Direct Digital Synthesis (DDS) Instrumentation PRODUCT DESCRIPTION 0.1 F 12-Bit, 125 MSPS TxDAC(R) D/A Converter AD9762* FUNCTIONAL BLOCK DIAGRAM +5V 0.1 F REFLO +1.20V REF 50pF REFIO FS ADJ RSET +5V DVDD DCOM CLOCK CLOCK SLEEP SEGMENTED SWITCHES COMP1 AVDD ACOM AD9762 CURRENT SOURCE ARRAY COMP2 0.1 F IOUTA LSB SWITCHES IOUTB LATCHES DIGITAL DATA INPUTS (DB11-DB0) The AD9762 is the 12-bit resolution member of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package and pinout, thus providing an upward or downward component selection path based on performance, resolution and cost. The AD9762 offers exceptional ac and dc performance while supporting update rates up to 125 MSPS. The AD9762's flexible single-supply operating range of 2.7 V to 5.5 V and low power dissipation are well suited for portable and low power applications. Its power dissipation can be further reduced to a mere 45 mW without a significant degradation in performance by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to approximately 25 mW. The AD9762 is manufactured on an advanced CMOS process. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered input latches and a 1.2 V temperature compensated bandgap reference have been integrated to provide a complete monolithic DAC solution. Flexible supply options support +3 V and +5 V CMOS logic families. The AD9762 is a current-output DAC with a nominal full-scale output current of 20 mA and > 100 k output impedance. TxDAC is a registered trademark of Analog Devices, Inc. *Patent pending. Differential current outputs are provided to support singleended or differential applications. Matching between the two current outputs ensures enhanced dynamic performance in a differential output configuration. The current outputs may be tied directly to an output resistor to provide two complementary, single-ended voltage outputs or fed directly into a transformer. The output voltage compliance range is 1.25 V. The on-chip reference and control amplifier are configured for maximum accuracy and flexibility. The AD9762 can be driven by the on-chip reference or by a variety of external reference voltages. The internal control amplifier which provides a wide (>10:1) adjustment span allows the AD9762 full-scale current to be adjusted over a 2 mA to 20 mA range while maintaining excellent dynamic performance. Thus, the AD9762 may operate at reduced power levels or be adjusted over a 20 dB range to provide additional gain ranging capabilities. The AD9762 is available in 28-lead SOIC and TSSOP packages. It is specified for operation over the industrial temperature range. PRODUCT HIGHLIGHTS REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 1. The AD9762 is a member of the TxDAC product family which provides an upward or downward component selection path based on resolution (8 to 14 bits), performance and cost. 2. Manufactured on a CMOS process, the AD9762 uses a proprietary switching technique that enhances dynamic performance beyond what was previously attainable by higher power/cost bipolar or BiCMOS devices. 3. On-chip, edge-triggered input CMOS latches interface readily to +3 V and +5 V CMOS logic families. The AD9762 can support update rates up to 125 MSPS. 4. A flexible single-supply operating range of 2.7 V to 5.5 V and a wide full-scale current adjustment span of 2 mA to 20 mA allow the AD9762 to operate at reduced power levels. 5. The current output(s) of the AD9762 can be easily configured for various single-ended or differential circuit topologies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000 AD9762-SPECIFICATIONS DC SPECIFICATIONS (T Parameter RESOLUTION DC ACCURACY1 Integral Linearity Error (INL) TA = +25C TMIN to TMAX Differential Nonlinearity (DNL) TA = +25C TMIN to TMAX ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance Small Signal Bandwidth (w/o CCOMP1)4 TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD5 DVDD Analog Supply Current (IAVDD) Digital Supply Current (IDVDD)6 Supply Current Sleep Mode (IAVDD) Power Dissipation6 (5 V, IOUTFS = 20 mA) Power Dissipation7 (5 V, IOUTFS = 20 mA) Power Dissipation7 (3 V, IOUTFS = 2 mA) Power Supply Rejection Ratio--AVDD Power Supply Rejection Ratio--DVDD OPERATING RANGE MIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted) Min 12 Typ Max Units Bits -2.5 -4.0 -1.5 -2.0 -0.025 -10 -10 2.0 -1.0 0.75 1.0 0.5 0.75 +2.5 +4.0 +1.5 +2.0 +0.025 +10 +10 20.0 +1.25 LSB LSB LSB LSB % of FSR % of FSR % of FSR mA V k pF V nA V M MHz ppm of FSR/C ppm of FSR/C ppm of FSR/C ppm/C 2 1 100 5 1.08 1.20 100 1.32 0.1 1 1.4 0 50 100 50 1.25 2.7 2.7 5.0 5.0 25 1.5 133 190 45 5.5 5.5 30 2 8.5 160 -0.4 -0.025 -40 +0.4 +0.025 +85 V V mA mA mA mW mW mW % of FSR/V % of FSR/V C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I OUTFS, is 32 x the IREF current. 3 Use an external buffer amplifier to drive any external load. 4 Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41. 5 For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance. 6 Measured at fCLOCK = 25 MSPS and fOUT = 1.0 MHz. 7 Measured as unbuffered voltage output into 50 RLOAD at IOUTA and IOUTB, f CLOCK = 100 MSPS and f OUT = 40 MHz. Specifications subject to change without notice. -2- REV. B AD9762 DYNAMIC SPECIFICATIONS 50 Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Output Settling Time (tST) (to 0.1%)1 Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%)1 Output Fall Time (10% to 90%)1 Output Noise (IOUTFS = 20 mA) Output Noise (IOUTFS = 2 mA) AC LINEARITY Spurious-Free Dynamic Range to Nyquist fCLOCK = 25 MSPS; fOUT = 1.00 MHz TA = +25C TMIN to TMAX fCLOCK = 50 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 2.51 MHz fCLOCK = 50 MSPS; fOUT = 5.02 MHz fCLOCK = 50 MSPS; fOUT = 20.2 MHz fCLOCK = 100 MSPS; fOUT = 2.51 MHz fCLOCK = 100 MSPS; fOUT = 5.04 MHz fCLOCK = 100 MSPS; fOUT = 20.2 MHz fCLOCK = 100 MSPS; fOUT = 40.4 MHz Spurious-Free Dynamic Range within a Window fCLOCK = 25 MSPS; fOUT =1.00 MHz; 2 MHz Span TA = +25C TMIN to TMAX fCLOCK = 50 MSPS; fOUT = 5.02 MHz; 2 MHz Span fCLOCK = 100 MSPS; fOUT = 5.04 MHz; 4 MHz Span Total Harmonic Distortion fCLOCK = 25 MSPS; fOUT = 1.00 MHz TA = +25C TMIN to TMAX fCLOCK = 50 MHz; fOUT = 2.00 MHz fCLOCK = 100 MHz; fOUT = 2.00 MHz Multitone Power Ratio (8 Tones at 110 kHz Spacing) fCLOCK = 20 MSPS; fOUT = 2.00 MHz to 2.99 MHz NOTES 1 Measured single ended into 50 load. Specifications subject to change without notice. (TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Differential Transformer Coupled Output, Doubly Terminated, unless otherwise noted) Min 125 35 1 5 2.5 2.5 50 30 Typ Max Units MSPS ns ns pV-s ns ns pA/Hz pA/Hz 75 73 79 79 74 70 57 73 67 57 53 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 78 76 86 84 84 dBc dBc dBc dBc -78 -75 -75 73 -74 -72 dBc dBc dBc dBc dBc REV. B -3- AD9762 DIGITAL SPECIFICATIONS (T Parameter DIGITAL INPUTS Logic "1" Voltage @ DVDD = +5 V Logic "1" Voltage @ DVDD = +3 V Logic "0" Voltage @ DVDD = +5 V Logic "0" Voltage @ DVDD = +3 V Logic "1" Current Logic "0" Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulsewidth (tLPW) Specifications subject to change without notice. MIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted) Min 3.5 2.1 Typ 5 3 0 0 Max Units V V V V A A pF ns ns ns -10 -10 5 2.0 1.5 3.5 1.3 0.9 +10 +10 DB0-DB11 tS CLOCK tH tLPW tPD tST 0.1% 0.1% IOUTA OR IOUTB Figure 1. Timing Diagram ABSOLUTE MAXIMUM RATINGS* Parameter AVDD DVDD ACOM AVDD CLOCK, SLEEP Digital Inputs IOUTA, IOUTB COMP1, COMP2 REFIO, FSADJ REFLO Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect to ACOM DCOM DCOM DVDD DCOM DCOM ACOM ACOM ACOM ACOM Min -0.3 -0.3 -0.3 -6.5 -0.3 -0.3 -1.0 -0.3 -0.3 -0.3 -65 Max +6.5 +6.5 +0.3 +6.5 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +0.3 +150 +150 +300 Units V V V V V V V V V V C C C ORDERING GUIDE Model Temperature Range Package Description Package Option* AD9762AR -40C to +85C 28-Lead 300 mil SOIC R-28 AD9762ARU -40C to +85C 28-Lead TSSOP RU-28 AD9762-EB Evaluation Board *R = SOIC, RU = TSSOP. THERMAL CHARACTERISTICS Thermal Resistance 28-Lead 300 mil SOIC JA = 71.4C/W JC = 23C/W 28-Lead TSSOP JA = 97.9C/W JC = 14.0C/W *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9762 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE -4- REV. B AD9762 PIN CONFIGURATION (MSB) DB11 1 DB10 2 DB9 3 DB8 4 DB7 5 DB6 6 28 CLOCK 27 DVDD 26 DCOM 25 NC AD9762 24 AVDD TOP VIEW 23 COMP2 DB5 7 (Not to Scale) 22 IOUTA DB4 8 DB3 9 DB2 10 DB1 11 DB0 12 NC 13 NC 14 21 IOUTB 20 ACOM 19 COMP1 18 FS ADJ 17 REFIO 16 REFLO 15 SLEEP NC = NO CONNECT PIN DESCRIPTIONS Pin No. 1 2-11 12 13, 14, 25 15 16 17 Name DB11 DB10-DB1 DB0 NC SLEEP REFLO REFIO Description Most Significant Data Bit (MSB). Data Bits 1-10. Least Significant Data Bit (LSB). No Internal Connection. Power-down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if not used. Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM). Requires 0.1 F capacitor to ACOM when internal reference activated. Full-Scale Current Output Adjust. Bandwidth/Noise Reduction Node. Add 0.1 F to AVDD for optimum performance. Analog Common. Complementary DAC Current Output. Full-scale current when all data bits are 0s. DAC Current Output. Full-scale current when all data bits are 1s. Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 F capacitor. Analog Supply Voltage (+2.7 V to +5.5 V). Digital Common. Digital Supply Voltage (+2.7 V to +5.5 V). Clock Input. Data latched on positive edge of clock. 18 19 20 21 22 23 24 26 27 28 FS ADJ COMP1 ACOM IOUTB IOUTA COMP2 AVDD DCOM DVDD CLOCK REV. B -5- AD9762 DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Power Supply Rejection Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (or DNL) The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Settling Time DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Glitch Impulse A D/A converter is monotonic if the output either increases or remains constant as the digital input increases. Offset Error Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Spurious-Free Dynamic Range The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Gain Error The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Total Harmonic Distortion The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. Output Compliance Range THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured output signal. It is expressed as a percentage or in decibels (dB). Multitone Power Ratio The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. Temperature Drift The spurious-free dynamic range for an output containing multiple carrier tones of equal amplitude. It is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone. Temperature drift is specified as the maximum change from the ambient (+25C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree C. For reference drift, the drift is reported in ppm per degree C. +5V 0.1 F REFLO +1.20V REF 0.1 F 50pF REFIO FS ADJ RSET 2k +5V DVDD DCOM CLOCK DVDD DCOM RETIMED CLOCK OUTPUT* LECROY 9210 PULSE GENERATOR 50 SLEEP COMP1 AVDD ACOM AD9762 PMOS CURRENT SOURCE ARRAY COMP2 0.1 F MINI-CIRCUITS T1-1T IOUTA 100 TO HP3589A SPECTRUM/ NETWORK ANALYZER 50 INPUT SEGMENTED SWITCHES FOR DB11-DB3 LATCHES LSB SWITCHES IOUTB 50 50 20pF 20pF CLOCK OUTPUT DIGITAL DATA TEKTRONIX AWG-2021 * AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK. Figure 2. Basic AC Characterization Test Set-Up -6- REV. B AD9762 Typical AC Characterization Curves @ +5 V Supplies (AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, 50 Doubly Terminated Load, Differential Output, TA = +25 C, SFDR up to Nyquist, unless otherwise noted) 85 80 80 5MSPS 50MSPS 70 25MSPS 90 -6dBFS 0dBFS 85 -6dBFS 80 -12dBFS 75 75 SFDR - dBc -12dBFS SFDR - dBc SFDR - dBc 70 65 60 55 50 0.00 70 0dBFS 65 60 55 50 0.00 2.00 100MSPS 60 125MSPS 50 0.1 1 10 FREQUENCY - MHz 100 0.50 1.00 1.50 2.00 FREQUENCY - MHz 2.50 4.00 6.00 8.00 10.00 12.00 FREQUENCY - MHz Figure 3. SFDR vs. fOUT @ 0 dBFS Figure 4. SFDR vs. fOUT @ 5 MSPS Figure 5. SFDR vs. fOUT @ 25 MSPS 85 80 75 SFDR - dBc 85 80 75 85 80 75 SFDR - dBc 70 65 60 0dBFS 55 0dBFS -6dBFS -6dBFS -12dBFS SFDR - dBc 70 65 0dBFS 60 55 50 0.00 70 -6dBFS 65 60 55 50 0.00 -12dBFS -12dBFS 5.00 10.00 15.00 20.00 FREQUENCY - MHz 25.00 10.00 20.00 30.00 40.00 FREQUENCY - MHz 50.00 50 0.00 10.00 20.00 30.00 40.00 50.00 60.00 FREQUENCY - MHz Figure 6. SFDR vs. fOUT @ 50 MSPS Figure 7. SFDR vs. fOUT @100 MSPS Figure 8. SFDR vs. fOUT @ 125 MSPS 85 455kHz @ 5MSPS 75 SFDR - dBc 85 1MHz @ 5MSPS 75 SFDR - dBc 80 0.675/0.725MHz @ 5MSPS 3.38/3.63MHz @ 25MSPS 2.27MHz @ 25MSPS 65 9.1MHz @ 100MSPS 11.37MHz @ 125MSPS 65 SFDR - dBc 4.55MHz @ 50MSPS 5.0MHz @ 25MSPS 10MHz @ 50MSPS 70 60 13.5/14.5MHz @ 100MSPS 50 6.75/7.25MHz @ 50MSPS 16.9/18.1MHz @ 125MSPS 55 55 25MHz @ 125MSPS 45 -30 20MHz @ 100MSPS 45 -30 -25 -20 -15 -10 AOUT - dBFS -5 0 -25 -20 -15 -10 AOUT - dBFS -5 0 40 -30 -25 -20 -15 -10 AOUT - dBFS -5 0 Figure 9. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/11 Figure 10. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/5 Figure 11. Dual-Tone SFDR vs. AOUT @ fOUT = fCLOCK/7 REV. B -7- AD9762 -70 80 75 2.5MHz 70 10MHz IDIFF @ -6dBFS 65 IOUTA @ 0dBFS 60 55 IOUTA @ -6dBFS 50 45 1 75 IDIFF @ 0dBFS -75 2ND HARMONIC -80 dBc 70 65 SFDR - dBc 60 55 50 45 3RD HARMONIC -85 40MHz -90 4TH HARMONIC -95 0 20 40 60 80 100 FREQUENCY - MSPS 120 140 40 35 30 2 4 6 8 10 12 14 IOUTFS - mA 16 18 20 SFDR - dBc 22.2MHz 10 OUTPUT FREQUENCY - MHz 100 Figure 12. THD vs. fCLOCK @ fOUT = 2 MHz Figure 13. SFDR vs. fOUT and IOUTFS @ 100 MSPS, 0 dBFS Figure 14. Differential vs. SingleEnded SFDR vs. fOUT @ 100 MSPS 1.25 1.00 0.75 0.50 1 0.8 0.6 80 75 70 2.5MHz ERROR - LSB ERROR - LSB 0.25 0 -0.25 -0.50 -0.75 -1.00 0.4 0.2 0 -0.2 -0.4 SFDR - dBc 65 60 55 10MHz 40MHz 0 1000 2000 CODE 3000 4000 -1.25 0 1000 2000 CODE 3000 4000 50 -40 -20 0 20 40 60 TEMPERATURE - C 80 Figure 15. Typical INL Figure 16. Typical DNL Figure 17. SFDR vs. Temperature @ 100 MSPS, 0 dBFS 0 fCLOCK = 100 MSPS fOUT = 2.41MHz SFDR = 72dBc AMPLITUDE = 0dBFS 0 fCLOCK = 100 MSPS fOUT1 = 13.5MHz fOUT2 = 14.5MHz SFDR = 62dBc AMPLITUDE = 0dBFS 10dB - Div -10 fCLOCK = 50 MSPS fOUT1 = 6.25MHz fOUT2 = 6.75MHz fOUT3 = 7.25MHz fOUT4 = 7.75MHz SFDR = 71dBc AMPLITUDE = 0dBFS 10dB - Div -100 START: 0.3 MHz STOP: 50.0 MHz -100 START: 0.3 MHz STOP: 50.0 MHz -110 START: 0.3 MHz STOP: 25.0 MHz Figure 18. Single-Tone SFDR Figure 19. Dual-Tone SFDR 10dB - Div Figure 20. Four-Tone SFDR -8- REV. B AD9762 Typical AC Characterization Curves @ +3 V Supplies (AVDD = +3 V, DVDD = +3 V, IOUTFS = 20 mA, 50 Doubly Terminated Load, Differential Output, TA = +25 C, SFDR up to Nyquist, unless otherwise noted) 90 85 80 80 5MSPS 25MSPS 70 50MSPS 100MSPS 60 125MSPS 50 0.1 SFDR - dBc 75 70 65 60 55 50 0.00 85 -6dBFS 80 -12dBFS 75 0dBFS SFDR - dBc SFDR - dBc -12dBFS 70 -6dBFS 65 60 55 50 0 0dBFS 1 10 FREQUENCY - MHz 100 0.50 1.00 1.50 2.00 FREQUENCY - MHz 2.50 2 4 6 8 FREQUENCY - MHz 10 12 Figure 21. SFDR vs. fOUT @ 0 dBFS Figure 22. SFDR vs. fOUT @ 5 MSPS Figure 23. SFDR vs. fOUT @ 25 MSPS 85 80 75 SFDR - dBc 85 80 -6dBFS SFDR - dBc 85 80 75 75 SFDR - dBc -12dBFS 70 65 60 55 50 0 0dBFS 70 65 60 55 50 0 -6dBFS -12dBFS 70 65 60 0dBFS -12dBFS 0dBFS -6dBFS 55 50 0 5 10 15 20 FREQUENCY - MHz 25 10 20 30 40 FREQUENCY - MHz 50 10 20 30 40 FREQUENCY - MHz 50 60 Figure 24. SFDR vs. fOUT @ 50 MSPS Figure 25. SFDR vs. fOUT @ 100 MSPS Figure 26. SFDR vs. fOUT @ 125 MSPS 90 90 455kHz @ 5MSPS 2.27MHz @ 25MSPS SFDR - dBc 90 1MHz @ 5MSPS 0.675/0.725MHz @ 5MSPS 80 SFDR - dBc 80 SFDR - dBc 4.55MHz @ 50MSPS 80 5.0MHz @ 25MSPS 70 10MHz @ 50MSPS 60 20MHz @ 100MSPS 25MHz @ 125MSPS 3.38/3.63MHz @ 25MSPS 70 6.75/7.25MHz @ 50MSPS 70 9.1MHz @ 100MSPS 11.37MHz @ 125MSPS 60 60 16.9/18.1MHz @ 125MSPS 50 13.5/14.5MHz @ 100MSPS -25 -20 -15 -10 AOUT - dBFS -5 0 50 50 40 -30 -25 -20 -15 -10 AOUT - dBFS -5 0 40 -30 -25 -20 -15 -10 AOUT - dBFS -5 0 40 -30 Figure 27. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/11 Figure 28. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/5 Figure 29. Dual-Tone SFDR vs. AOUT @ fOUT = fCLOCK/7 REV. B -9- AD9762 -70 80 75 2.5MHz 70 10MHz 22.2MHz 55 50 40MHz 45 40 35 SFDR - dBc 65 60 55 50 IOUTA @ 0dBFS 2 4 6 8 10 12 14 IOUTFS - mA 16 18 20 45 1 10 OUTPUT FREQUENCY - MHz 100 IOUTA @ -6dBFS IDIFF @ -6dBFS 75 -75 2ND HARMONIC 70 SFDR - dBc -80 dBc 3RD HARMONIC 65 60 -85 IDIFF @ 0dBFS -90 4TH HARMONIC -95 0 20 40 60 80 100 FREQUENCY - MSPS 120 140 30 Figure 30. THD vs. fCLOCK @ fOUT = 2 MHz Figure 31. SFDR vs. fOUT and IOUTFS @ 100 MSPS, 0 dBFS Figure 32. Differential vs. Single Ended SFDR vs. fOUT @ 100 MSPS 1.25 1.00 0.75 0.50 ERROR - LSB 1 0.8 0.6 80 75 2.5MHz ERROR - LSB 70 0.4 0.2 0 -0.2 0.25 0 -0.25 -0.50 -0.75 -1.00 -1.25 0 1000 2000 CODE 3000 4000 SFDR - dBc 65 10MHz 60 55 28.6MHz -20 0 20 40 60 TEMPERATURE - C 80 -0.4 0 1000 2000 CODE 3000 4000 50 -40 Figure 33. Typical INL Figure 34. Typical DNL Figure 35. SFDR vs. Temperature @ 100 MSPS, 0 dBFS 0 fCLOCK = 100 MSPS fOUT = 2.41MHz SFDR = 72dBc AMPLITUDE = 0dBFS 10dB - Div 0 fCLOCK = 100 MSPS fOUT1 = 13.5MHz fOUT2 = 14.5MHz SFDR = 59.0dBc AMPLITUDE = 0dBFS -10 fCLOCK = 50 MSPS fOUT1 = 6.25MHz fOUT2 = 6.75MHz fOUT3 = 7.25MHz fOUT4 = 7.75MHz SFDR = 71dBc AMPLITUDE = 0dBFS 10dB - Div -100 START: 0.3 MHz STOP: 50.0 MHz -100 START: 0.3 MHz STOP: 50.0 MHz -110 START: 0.3 MHz STOP: 25.0 MHz Figure 36. Single-Tone SFDR Figure 37. Dual-Tone SFDR 10dB - Div Figure 38. Four-Tone SFDR -10- REV. B AD9762 FUNCTIONAL DESCRIPTION Figure 39 shows a simplified block diagram of the AD9762. The AD9762 consists of a large PMOS current source array that is capable of providing up to 20 mA of total current. The array is divided into 31 equal currents that make up the 5 most significant bits (MSBs). The next 4 bits or middle bits consist of 15 equal current sources whose value is 1/16th of an MSB current source. The remaining LSBs are binary weighted fractions of the middle-bits current sources. Implementing the middle and lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the DAC's high output impedance (i.e., >100 k). All of these current sources are switched to one or the other of the two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. The switches are based on a new architecture that drastically improves distortion performance. This new switch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. The analog and digital sections of the AD9762 have separate power supply inputs (i.e., AVDD and DVDD) that can operate independently over a 2.7 volt to 5.5 volt range. The digital section, which is capable of operating up to a 125 MSPS clock rate, consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1.20 V bandgap voltage reference and a reference control amplifier. The full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an external resistor, RSET. The external resistor, in combination with both the reference control amplifier and voltage reference VREFIO, sets the reference current IREF, which is mirrored over to the segmented current sources with the proper scaling factor. The full-scale current, IOUTFS, is thirty-two times the value of IREF. DAC TRANSFER FUNCTION IOUTA = (DAC CODE/4096) x IOUTFS IOUTB = (4095 - DAC CODE)/4096 x IOUTFS (1) (2) where DAC CODE = 0 to 4095 (i.e., Decimal Representation). As mentioned previously, IOUTFS is a function of the reference current IREF, which is nominally set by a reference voltage VREFIO and external resistor RSET. It can be expressed as: IOUTFS = 32 x IREF where IREF = VREFIO/RSET (3) (4) The two current outputs will typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads, RLOAD, which are tied to analog common, ACOM. Note, RLOAD may represent the equivalent load resistance seen by IOUTA or IOUTB as would be the case in a doubly terminated 50 or 75 cable. The single-ended voltage output appearing at the IOUTA and IOUTB nodes is simply : VOUTA = IOUTA x RLOAD VOUTB = IOUTB x RLOAD (5) (6) Note the full-scale value of VOUTA and VOUTB should not exceed the specified output compliance range to maintain specified distortion and linearity performance. The differential voltage, VDIFF, appearing across IOUTA and IOUTB is: VDIFF = (IOUTA - IOUTB) x RLOAD (7) Substituting the values of IOUTA, IOUTB, and IREF; VDIFF can be expressed as: VDIFF = {(2 DAC CODE - 4095)/4096} x (32 RLOAD/RSET) x VREFIO (8) The AD9762 provides complementary current outputs, IOUTA and IOUTB. IOUTA will provide a near full-scale current output, IOUTFS, when all bits are high (i.e., DAC CODE = 4095) while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB is a function of both the input code and IOUTFS and can be expressed as: These last two equations highlight some of the advantages of operating the AD9762 differentially. First, the differential operation will help cancel common-mode error sources associated with IOUTA and IOUTB such as noise, distortion and dc offsets. Second, the differential code dependent current and subsequent voltage, VDIFF, is twice the value of the single-ended voltage output (i.e., VOUTA or VOUTB), thus providing twice the signal power to the load. Note, the gain drift temperature performance for a single-ended (VOUTA and VOUTB) or differential output (VDIFF) of the AD9762 can be enhanced by selecting temperature tracking resistors for RLOAD and RSET due to their ratiometric relationship as shown in Equation 8. +5V 0.1 F REFLO +1.20V REF VREFIO 0.1 F RSET 2k IREF +5V REFIO FS ADJ DVDD DCOM CLOCK CLOCK SLEEP 50pF COMP1 AVDD ACOM AD9762 PMOS CURRENT SOURCE ARRAY COMP2 0.1 F VDIFF = VOUTA - VOUTB IOUTA IOUTA IOUTB VOUTB RLOAD 50 VOUTA RLOAD 50 SEGMENTED SWITCHES FOR DB11-DB3 LATCHES LSB SWITCHES IOUTB DIGITAL DATA INPUTS (DB11-DB0) REV. B Figure 39. Functional Block Diagram -11- AD9762 REFERENCE OPERATION The AD9762 contains an internal 1.20 V bandgap reference that can be easily disabled and overridden by an external reference. REFIO serves as either an input or output depending on whether the internal or an external reference is selected. If REFLO is tied to ACOM, as shown in Figure 40, the internal reference is activated and REFIO provides a 1.20 V output. In this case, the internal reference must be compensated externally with a ceramic chip capacitor of 0.1 F or greater from REFIO to REFLO. Also, REFIO should be buffered with an external amplifier having an input bias current less than 100 nA if any additional loading is required. +5V OPTIONAL EXTERNAL REF BUFFER 0.1 F The control amplifier allows a wide (10:1) adjustment span of IOUTFS over a 2 mA to 20 mA range by setting IREF between 62.5 A and 625 A. The wide adjustment span of IOUTFS provides several application benefits. The first benefit relates directly to the power dissipation of the AD9762, which is proportional to IOUTFS (refer to the Power Dissipation section). The second benefit relates to the 20 dB adjustment, which is useful for system gain control purposes. The small signal bandwidth of the reference control amplifier is approximately 1.4 MHz and can be reduced by connecting an external capacitor between COMP1 and AVDD. The output of the control amplifier, COMP1, is internally compensated via a 50 pF capacitor that limits the control amplifier small-signal bandwidth and reduces its output impedance. Any additional external capacitance further limits the bandwidth and acts as a filter to reduce the noise contribution from the reference amplifier. Figure 42 shows the relationship between the external capacitor and the small signal -3 dB bandwidth of the 1000 REFLO +1.2V REF 50pF REFIO COMP1 AVDD ADDITIONAL LOAD 0.1 F 2k FS ADJ CURRENT SOURCE ARRAY AD9762 The internal reference can be disabled by connecting REFLO to AVDD. In this case, an external reference may then be applied to REFIO as shown in Figure 41. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1 F compensation capacitor is not required since the internal reference is disabled, and the high input impedance (i.e., 1 M) of REFIO minimizes any loading of the external reference. AVDD 0.1 F BANDWIDTH - kHz Figure 40. Internal Reference Configuration 10 0 0.1 1 10 COMP1 CAPACITOR - nF 100 1000 Figure 42. External COMP1 Capacitor vs. -3 dB Bandwidth AVDD VREFIO REFLO +1.2V REF 50pF REFIO FS ADJ RSET IREF = VREFIO/RSET COMP1 AVDD reference amplifier. Since the -3 dB bandwidth corresponds to the dominant pole, and hence the time constant, the settling time of the control amplifier to a stepped reference input response can be approximated. The optimum distortion performance for any reconstructed waveform is obtained with a 0.1 F external capacitor installed. Thus, if IREF is fixed for an application, a 0.1 F ceramic chip capacitor is recommended. Also, since the control amplifier is optimized for low power operation, multiplying applications requiring large signal swings should consider using an external control amplifier to enhance the application's overall large signal multiplying bandwidth and/or distortion performance. There are two methods in which IREF can be varied for a fixed RSET. The first method is suitable for a single-supply system in which the internal reference is disabled, and the common-mode voltage of REFIO is varied over its compliance range of 1.25 V to 0.10 V. REFIO can be driven by a single-supply amplifier or DAC, thus allowing IREF to be varied for a fixed RSET. Since the input impedance of REFIO is approximately 1 M, a simple, low cost R-2R ladder DAC configured in the voltage mode topology may be used to control the gain. This circuit is shown in Figure 43 using the AD7524 and an external 1.2 V reference, the AD1580. EXTERNAL REF CURRENT SOURCE ARRAY REFERENCE CONTROL AMPLIFIER AD9762 Figure 41. External Reference Configuration REFERENCE CONTROL AMPLIFIER The AD9762 also contains an internal control amplifier that is used to regulate the DAC's full-scale output current, IOUTFS. The control amplifier is configured as a V-I converter as shown in Figure 41, such that its current output, IREF, is determined by the ratio of the VREFIO and an external resistor, RSET, as stated in Equation 4. IREF is copied over to the segmented current sources with the proper scaling factor to set IOUTFS as stated in Equation 3. -12- REV. B AD9762 AVDD AVDD OPTIONAL BANDLIMITING CAPACITOR REFLO RFB 1.2V OUT1 VDD VREF 0.1V TO 1.2V +1.2V REF 50pF REFIO FS ADJ AGND RSET DB7-DB0 IREF = VREF/RSET CURRENT SOURCE ARRAY COMP1 AVDD AD7524 AD1580 OUT2 AD9762 Figure 43. Single-Supply Gain Control Circuit The second method may be used in a dual-supply system in which the common-mode voltage of REFIO is fixed and IREF is varied by an external voltage, VGC, applied to RSET via an amplifier. An example of this method is shown in Figure 44 in which the internal reference is used to set the common-mode voltage of the control amplifier to 1.20 V. The external voltage, VGC, is referenced to ACOM and should not exceed 1.2 V. The value of RSET is such that IREFMAX and IREFMIN do not exceed 62.5 A and 625 A, respectively. The associated equations in Figure 44 can be used to determine the value of RSET. OPTIONAL BANDLIMITING CAPACITOR AVDD ANALOG OUTPUTS The AD9762 produces two complementary current outputs, IOUTA and IOUTB, which may be configured for single-ended or differential operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in the DAC Transfer Function section by Equations 5 through 8. The differential voltage, VDIFF, existing between VOUTA and VOUTB can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. The ac performance of the AD9762 is optimum and specified using a differential transformer coupled output in which the voltage swing at IOUTA and IOUTB is limited to 0.5 V. If a single-ended unipolar output is desirable, IOUTA should be selected. The distortion and noise performance of the AD9762 can be enhanced when the AD9762 is configured for differential operation. The common-mode error sources of both IOUTA and IOUTB can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases. This is due to the first order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough and noise. Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (i.e., assuming no source termination). Since the output currents of IOUTA and IOUTB are complementary, they become additive when processed differentially. A properly selected transformer will allow the AD9762 to provide the required power and voltage levels to different loads. Refer to Applying the AD9762 section for examples of various output configurations. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 k in parallel with 5 pF. It is also slightly dependent on the output voltage (i.e., VOUTA and VOUTB) due to the nature of a PMOS device. As a result, maintaining IOUTA and/or IOUTB at a virtual ground via an I-V op amp configuration will result in the optimum dc linearity. Note, the INL/DNL specifications for the AD9762 are measured with IOUTA maintained at a virtual ground via an op amp. REFLO +1.2V REF REFIO 1F RSET IREF COMP1 AVDD 50pF CURRENT SOURCE ARRAY FS ADJ AD9762 IREF 625A VGC IREF = (1.2-VGC)/RSET WITH VGC < VREFIO AND 62.5 A Figure 44. Dual-Supply Gain Control Circuit In some applications, the user may elect to use an external control amplifier to enhance the multiplying bandwidth, distortion performance, and/or settling time. External amplifiers capable of driving a 50 pF load such as the AD817 are suitable for this purpose. It is configured in such a way that it is in parallel with the weaker internal reference amplifier as shown in Figure 45. In this case, the external amplifier simply overdrives the weaker reference control amplifier. Also, since the internal control amplifier has a limited current output, it will sustain no damage if overdriven. EXTERNAL CONTROL AMPLIFIER VREF INPUT REFLO +1.2V REF REFIO FS ADJ RSET 50pF CURRENT SOURCE ARRAY COMP1 AVDD AVDD AD9762 Figure 45. Configuring an External Reference Control Amplifier REV. B -13- AD9762 IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of -1.0 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9762. The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS = 2 mA. The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUTA and IOUTB does not exceed 0.5 V. Applications requiring the AD9762's output (i.e., VOUTA and/ or VOUTB) to extend its output compliance range should size RLOAD accordingly. Operation beyond this compliance range will adversely affect the AD9762's linearity performance and subsequently degrade its distortion performance. DIGITAL INPUTS Since the AD9762 is capable of being updated up to 125 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. The drivers of the digital data interface circuitry should be specified to meet the minimum set-up and hold times of the AD9762 as well as its required min/max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above conditions will result in the lowest data feedthrough and noise. Digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. The insertion of a low value resistor network (i.e., 20 to 100 ) between the AD9762 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to data feedthrough. For longer run lengths and high data update rates, strip line techniques with proper termination resistors should be considered to maintain "clean" digital inputs. Also, operating the AD9762 with reduced logic swings and a corresponding digital supply (DVDD) will also reduce data feedthrough. The external clock driver circuitry should provide the AD9762 with a low jitter clock input meeting the min/max logic levels while providing fast edges. Fast clock edges will help minimize any jitter that will manifest itself as phase noise on a reconstructed waveform. Thus, the clock input should be driven by the fastest logic family suitable for the application. Note, the clock input could also be driven via a sine wave, which is centered around the digital threshold (i.e., DVDD/2), and meets the min/max logic threshold. This will typically result in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. Also, at higher sampling rates, the 20% tolerance of the digital logic threshold should be considered since it will affect the effective clock duty cycle and subsequently cut into the required data set-up and hold times. SLEEP MODE OPERATION The AD9762's digital input consists of 12 data input pins and a clock input pin. The 12-bit parallel data inputs follow standard positive binary coding where DB11 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). IOUTA produces a full-scale output current when all data bits are at Logic 1. IOUTB produces a complementary output with the full-scale current split between the two outputs as a function of the input code. The digital interface is implemented using an edge-triggered master slave latch. The DAC output is updated following the rising edge of the clock as shown in Figure 1 and is designed to support a clock rate as high as 125 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulsewidth. The set-up and hold times can also be varied within the clock cycle as long as the specified minimum times are met; although the location of these transition edges may affect digital feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. The digital inputs are CMOS compatible with logic thresholds, VTHRESHOLD set to approximately half the digital positive supply (DVDD) or VTHRESHOLD = DVDD/2 ( 20%) The internal digital circuitry of the AD9762 is capable of operating over a digital supply range of 2.7 V to 5.5 V. As a result, the digital inputs can also accommodate TTL levels when DVDD is set to accommodate the maximum high level voltage of the TTL drivers VOH(MAX). A DVDD of 3 V to 3.3 V will typically ensure proper compatibility with most TTL logic families. Figure 46 shows the equivalent digital input circuit for the data and clock inputs. The sleep mode input is similar with the exception that it contains an active pull-down circuit, thus ensuring that the AD9762 remains enabled if this input is left disconnected. DVDD The AD9762 has a power-down function which turns off the output current and reduces the supply current to less than 8.5 mA over the specified supply range of 2.7 V to 5.5 V and temperature range. This mode can be activated by applying a logic level "1" to the SLEEP pin. This digital input also contains an active pull-down circuit that ensures the AD9762 remains enabled if this input is left disconnected. The SLEEP input with active pull-down requires <40 A of drive current. The power-up and power-down characteristics of the AD9762 are dependent upon the value of the compensation capacitor connected to COMP1. With a nominal value of 0.1 F, the AD9762 takes less than 5 s to power down and approximately 3.25 ms to power back up. Note, the SLEEP MODE should not be used when the external control amplifier is used as shown in Figure 45. POWER DISSIPATION DIGITAL INPUT Figure 46. Equivalent Digital Input The power dissipation, PD, of the AD9762 is dependent on several factors which include: (1) AVDD and DVDD, the power supply voltages; (2) IOUTFS, the full-scale current output; (3) fCLOCK, the update rate; (4) and the reconstructed digital input waveform. The power dissipation is directly proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS as shown in Figure 47 and is insensitive to fCLOCK. -14- REV. B AD9762 30 APPLYING THE AD9762 OUTPUT CONFIGURATIONS 25 20 IAVDD - mA 15 10 5 0 The following sections illustrate some typical output configurations for the AD9762. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 20 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application allowing for ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain and/or level shifting. 2 4 6 8 10 12 IOUTFS - mA 14 16 18 20 Figure 47. IAVDD vs. IOUTFS Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply DVDD. Figures 48 and 49 show IDVDD as a function of full-scale sine wave output ratios (fOUT/fCLOCK) for various update rates with DVDD = 5 V and DVDD = 3 V, respectively. Note, how IDVDD is reduced by more than a factor of 2 when DVDD is reduced from 5 V to 3 V. 18 125MSPS 16 A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage will result if IOUTA and/or IOUTB is connected to an appropriately sized load resistor, RLOAD, referred to ACOM. This configuration may be more suitable for a single-supply system requiring a dc coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter thus converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity since IOUTA or IOUTB is maintained at a virtual ground. Note, IOUTA provides slightly better performance than IOUTB. DIFFERENTIAL COUPLING USING A TRANSFORMER 14 12 IDVDD - mA 10 8 100MSPS 50MSPS 6 4 2 5MSPS 0 0.01 0.1 RATIO (fOUT/fCLK) 1 25MSPS An RF transformer can be used to perform a differential-tosingle-ended signal conversion as shown in Figure 50. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer's passband. An RF transformer such as the Mini-Circuits T1-1T provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for impedance matching purposes. Note that the transformer provides ac coupling only. MINI-CIRCUITS T1-1T IOUTA 22 Figure 48. IDVDD vs. Ratio @ DVDD = 5 V 8 125MSPS AD9762 IOUTB 21 OPTIONAL RDIFF RLOAD 6 100MSPS IDVDD - mA Figure 50. Differential Output Using a Transformer 4 50MSPS 2 25MSPS 0 0.01 5MSPS 0.1 RATIO (fOUT/fCLK) 1 Figure 49. IDVDD vs. Ratio @ DVDD = 3 V The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9762. A differential resistor, RDIFF, may be inserted in applications in which the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF is determined by the transformer's impedance ratio and provides the proper source termination which results in a low VSWR. Note that approximately half the signal power will be dissipated across RDIFF. REV. B -15- AD9762 DIFFERENTIAL USING AN OP AMP An op amp can also be used to perform a differential to singleended conversion as shown in Figure 51. The AD9762 is configured with two equal load resistors, RLOAD, of 25 . The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amps distortion performance by preventing the DACs high slewing output from overloading the op amp's input. 500 this mode is the integral nonlinearity (INL) as discussed in the Analog Output section of this data sheet. For optimum INL performance, the single-ended, buffered voltage output configuration is suggested. AD9762 IOUTA 22 50 IOUTB 21 25 IOUTFS = 20mA VOUTA = 0 TO +0.5V 50 AD9762 225 IOUTA 22 225 IOUTB 21 COPT 500 25 25 Figure 53. 0 V to +0.5 V Unbuffered Voltage Output SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION AD8047 Figure 51. DC Differential Coupling Using an Op Amp The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8047 is configured to provide some additional signal gain. The op amp must operate off of a dual supply since its output is approximately 1.0 V. A high speed amplifier capable of preserving the differential performance of the AD9762 while meeting other system level objectives (i.e., cost, power) should be selected. The op amps differential gain, its gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. The differential circuit shown in Figure 52 provides the necessary level-shifting required in a single supply system. In this case, AVDD which is the positive analog supply for both the AD9762 and the op amp is also used to level-shift the differential output of the AD9762 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. 500 Figure 54 shows a buffered single-ended output configuration in which the op amp U1 performs an I-V conversion on the AD9762 output current. U1 maintains IOUTA (or IOUTB) at a virtual ground, thus minimizing the nonlinear output impedance effect on the DAC's INL performance as discussed in the Analog Output section. Although this single-ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates may be limited by U1's slewing capabilities. U1 provides a negative unipolar output voltage and its full-scale output voltage is simply the product of RFB and IOUTFS. The full-scale output should be set within U1's voltage output swing capabilities by scaling IOUTFS and/or RFB. An improvement in ac distortion performance may result with a reduced IOUTFS since the signal current U1 will be required to sink will be subsequently reduced. COPT RFB 200 AD9762 IOUTA 22 IOUTFS = 10mA U1 IOUTB 21 200 VOUT = IOUTFS RFB AD9762 225 IOUTA 22 225 IOUTB 21 COPT 25 25 1k Figure 54. Unipolar Buffered Voltage Output AD8041 1k AVDD POWER AND GROUNDING CONSIDERATIONS Figure 52. Single-Supply DC Differential Coupled Circuit SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT Figure 53 shows the AD9762 configured to provide a unipolar output range of approximately 0 V to +0.5 V for a doubly terminated 50 cable since the nominal full-scale current, IOUTFS, of 20 mA flows through the equivalent RLOAD of 25 . In this case, RLOAD represents the equivalent load resistance seen by IOUTA or IOUTB. The unused output (IOUTA or IOUTB) can be connected to ACOM directly or via a matching RLOAD. Different values of IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to. One additional consideration in In systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. Proper RF techniques must be used in device selection; placement and routing; and supply bypassing and grounding. Figures 60-65 illustrate the recommended printed circuit board ground, power and signal plane layouts which are implemented on the AD9762 evaluation board. Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9762 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as physically possible. Similarly, DVDD, the digital supply, should be decoupled to DCOM as close as physically as possible. REV. B -16- AD9762 For those applications that require a single +5 V or +3 V supply for both the analog and digital supply, a clean analog supply may be generated using the circuit shown in Figure 55. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained using low ESR type electrolytic and tantalum capacitors. FERRITE BEADS TTL/CMOS LOGIC CIRCUITS AVDD 100 F ELECT. 10-22 F TANT. 0.1 F CER. ACOM APPLICATIONS Using the AD9762 for QAM Modulation QAM is one of the most widely used digital modulation schemes in digital communication systems. This modulation technique can be found in both FDM as well as spreadspectrum (i.e., CDMA) based systems. A QAM signal is a carrier frequency which is both modulated in amplitude (i.e., AM modulation) and in phase (i.e., PM modulation). It can be generated by independently modulating two carriers of identical frequency but with a 90 phase difference. This results in an in-phase (I) carrier component and a quadrature (Q) carrier component at a 90 phase shift with respect to the I component. The I and Q components are then summed to provide a QAM signal at the specified carrier frequency. A common and traditional implementation of a QAM modulator is shown in Figure 56. The modulation is performed in the analog domain in which two DACs are used to generate the baseband I and Q components, respectively. Each component is then typically applied to a Nyquist filter before being applied to a quadrature mixer. The matching Nyquist filters shape and limit each component's spectral envelope while minimizing intersymbol interference. The DAC is typically updated at the QAM symbol rate or possibly a multiple of it if an interpolating filter precedes the DAC. The use of an interpolating filter typically eases the implementation and complexity of the analog filter, which can be a significant contributor to mismatches in gain and phase between the two baseband channels. A quadrature mixer modulates the I and Q components with in-phase and quadrature phase carrier frequency and then sums the two outputs to provide the QAM signal. 12 +5V OR +3V POWER SUPPLY Figure 55. Differential LC Filter for Single +5 V or +3 V Applications Maintaining low noise on power supplies and ground is critical to obtaining optimum results from the AD9762. If properly implemented, ground planes can perform a host of functions on high speed circuit boards: bypassing, shielding, current transport, etc. In mixed signal design, the analog and digital portions of the board should be distinct from each other, with the analog ground plane confined to the areas covering the analog signal traces, and the digital ground plane confined to areas covering the digital interconnects. All analog ground pins of the DAC, reference and other analog components should be tied directly to the analog ground plane. The two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the DAC to maintain optimum performance. Care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. On the digital side, this includes the digital input lines running to the DAC as well as any clock signals. On the analog side, this includes the DAC output signal, reference signal and the supply feeders. The use of wide runs or planes in the routing of power lines is also recommended. This serves the dual role of providing a low series impedance power supply to the part, as well as providing some "free" capacitive decoupling to the appropriate ground plane. It is essential that care be taken in the layout of signal and power ground interconnects to avoid inducing extraneous voltage drops in the signal ground paths. It is recommended that all connections be short, direct and as physically close to the package as possible in order to minimize the sharing of conduction paths between different currents. When runs exceed an inch in length, strip line techniques with proper termination resistor should be considered. The necessity and value of this resistor will be dependent upon the logic family used. For a more detailed discussion of the implementation and construction of high speed, mixed signal printed circuit boards, refer to Analog Devices' application notes AN-280 and AN-333. AD9762 DSP OR ASIC 12 CARRIER FREQUENCY 0 90 TO MIXER AD9762 NYQUIST FILTERS QUADRATURE MODULATOR Figure 56. Typical Analog QAM Architecture In this implementation, it is much more difficult to maintain proper gain and phase matching between the I and Q channels. The circuit implementation shown in Figure 57 helps improve upon the matching and temperature stability characteristics between the I and Q channels. Using a single voltage reference derived from U1 to set the gain for both the I and Q channels will improve the gain matching and stability. Further enhancements in gain matching and stability are achieved by using separate matching resistor networks for both RSET and RLOAD. Additional trim capability via RCAL1 and RCAL2 can be added to compensate for any initial mismatch in gain between the two channels. This may be attributed to any mismatch between U1 and U2's gain setting resistor, (RSET); effective load resistance, (RLOAD); and/or voltage offset of each DAC's control amplifier. The differential voltage outputs of U1 and U2 are fed into their respective differential inputs of a quadrature mixer via matching 50 filter networks. REV. B -17- AD9762 AD9762 EVALUATION BOARD General Description REFIO FS ADJ REFLO U1 I-CHANNEL IOUTA IOUTB 50 ** RLOAD 50 ** RLOAD RSET 2k * RCAL1 50 CLOCK CLOCK AVDD TO NYQUIST FILTER AND MIXER The AD9762-EB is an evaluation board for the AD9762 12-bit D/A converter. Careful attention to layout and circuit design combined with a prototyping area allow the user to easily and effectively evaluate the AD9762 in any application where high resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9762 in various configurations. Possible output configurations include transformer coupled, resistor terminated, inverting/noninverting and differential amplifier outputs. The digital inputs are designed to be driven directly from various word generators, with the on-board option to add a resistor network for proper load termination. Provisions are also made to operate the AD9762 with either the internal or external reference, or to exercise the power-down feature. Refer to the application note AN-420 "Using the AD9760/ AD9762/AD9764-EB Evaluation Board" for a thorough description and operating instructions for the AD9762 evaluation board. REFLO REFIO 0.1 F RSET 2k * RCAL2 100 FS ADJ CLOCK IOUTA IOUTB 50 ** RLOAD 50 ** RLOAD U2 Q-CHANNEL TO NYQUIST FILTER AND MIXER * OHMTEK ORNA1001F ** OHMTEK TOMC1603-50F Figure 57. Baseband QAM Implementation Using Two AD9762s It is also possible to generate a QAM signal completely in the digital domain via a DSP or ASIC, in which case only a single DAC of sufficient resolution and performance is required to reconstruct the QAM signal. Also available from several vendors are Digital ASICs which implement other digital modulation schemes such as PSK and FSK. This digital implementation has the benefit of generating perfectly matched I and Q components in terms of gain and phase, which is essential in maintaining optimum performance in a communication system. In this implementation, the reconstruction DAC must be operating at a sufficiently high clock rate to accommodate the highest specified QAM carrier frequency. Figure 58 shows a block diagram of such an implementation using the AD9762. 12 I DATA Q DATA 12 STEL-1130 QAM LPF 12 TO MIXER AD9762 12 SIN 12 COS 50 50 CARRIER 12 FREQUENCY STEL-1177 NCO CLOCK Figure 58. Digital QAM Architecture -18- REV. B REV. B AVDD AGND B3 B4 TP19 TP6 TP7 TP18 TP5 C4 10 F A A A DVDD B5 B6 DGND AVEE AVCC B1 TP4 B2 TP3 TP2 J1 A EXTCLK 1 2 3 R15 49.9 B C3 10 F DVDD R3 16 PINDIP RES PK 1 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 1 U1 AVDD C7 1F C8 0.1 F A C5 10 F C6 10 F TP1 CLK JP1 DVDD R7 R1 R5 1 2 3 4 5 6 7 8 9 10 1 TP8 C9 0.1 F P1 2 3 4 5 6 7 8 9 10 AD976x AVDD OUT 1 OUT 2 C19 C1 C2 C25 C26 C27 C28 C29 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 16 PINDIP RES PK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CLOCK DVDD DCOM NC AVDD COMP2 IOUTA IOUTB ACOM COMP1 FS ADJ REFIO REFLO SLEEP TP11 A 28 27 26 25 24 23 22 21 20 19 18 17 16 15 TP10 AVDD R16 2k 1 2 JP2 3 C11 0.1 F TP14 TP9 TP13 CT1 A 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 C30 C31 C32 C33 C34 C35 C36 1 2 3 4 5 6 7 10 9 8 7 6 5 4 3 2 1 R4 R8 DVDD DVDD 1 1 R17 49.9 10 9 8 7 6 5 4 3 2 16 15 14 13 12 11 10 JP4 PDIN J2 TP12 A A A 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 C10 0.1 F Figure 59. AD9762 Evaluation Board Schematic R18 1k A -19- AVCC JP6A JP7B JP7A JP8 R12 OPEN B R10 1k B B C20 0 A 10 9 8 7 6 5 4 3 2 10 9 8 7 6 5 4 3 2 AVDD 1 R2 R6 J3 U4 3 AVCC C21 0.1 F 7 A U7 C22 1F J6 2 6 AVCC OUT1 J7 2 REF43 VIN VOUT GND 6 R42 1k U6 3 C17 0.1 F JP3 2 1 B R20 49.9 C12 22pF T1 AD8047 4 C18 0.1 F R37 49.9 A A C16 1F 4 A 3 R43 5k CW 2 A A 7 6 4 A JP6B A A A A 3 AD8047 A R14 0 5 4 R36 1k EXTREFIN J5 C14 1F R35 1k JP5 R45 1k C23 0.1 F C24 1F R44 50 A AVEE A 1 A JP9 A 6 A A 3 2 1 C15 0.1 F A J4 R13 OPEN R9 1k OUT2 B A A R46 1k AVEE A R38 49.9 C13 22pF AD9762 A A AD9762 Figure 60. Silkscreen Layer--Top Figure 61. Component Side PCB Layout (Layer 1) -20- REV. B AD9762 Figure 62. Ground Plane PCB Layout (Layer 2) Figure 63. Power Plane PCB Layout (Layer 3) REV. B -21- AD9762 Figure 64. Solder Side PCB Layout (Layer 4) Figure 65. Silkscreen Layer--Bottom -22- REV. B AD9762 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70) 28 15 0.2992 (7.60) 0.2914 (7.40) 1 14 0.4193 (10.65) 0.3937 (10.00) PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) 0.0098 (0.25) 45 0.0118 (0.30) 0.0040 (0.10) 0.0500 (1.27) BSC 8 0 0.0192 (0.49) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 28-Lead, TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 14 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX SEATING PLANE 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 8 0 0.028 (0.70) 0.020 (0.50) REV. B -23- PRINTED IN U.S.A. C2201b-1-3/00 (rev. B) |
Price & Availability of AD9762
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